(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating an alignment mark that is used to align wafers.
(2) Description of the Prior Art
During the process of creating semiconductor devices, many interacting technologies are applied that collectively lead to devices of various complexity. In many of the processing steps that are used for the creation of a semiconductor device, masks are used to expose patterns on a semiconductor surface. In the creation of overlying patterns it is of extreme importance that not only the resolution for the creation of a pattern is optimized but that, in addition, overlay accuracy is tightly controlled. Overlay inaccuracy can be introduced during the alignment of an exposure mask and during the subsequent exposure process. The literature of the art offers numerous and excellent documentation relating to wafer exposure, the methods used, sources of error that can be introduced for each of the methods used and the like. In view of the ready availability of such documentation, only a summary overview will be presented here while further detailed insight can readily be gained from the available literature. The below referenced and related patents offer a good starting point for further reference, this starting point provides adequate material for further detail on the subject of wafer overlay accuracy.
One of the sources of reference on the subject of overlay accuracy is the textbook ULSI Technology by Chang and Sze, which is a well-known reference book in the art. Chang and Sze offer an overview of overlay accuracy, section 6.2.4, page 288 of the referenced volume. Chang and Sze provide detail regarding methods of alignment (off-axis and through-the-lens or TTL), advantages of the off-axis method (using nonactinic rays and broad-band and high NA viewing with the therefrom following brightfield, darkfield or phase-contrast viewing, easy upgrading of the system), disadvantages of the off-axis system (requiring high mechanical stability and accurate means to refer the positions of the interacting components of mask, wafer and the alignment microscope) in addition to advantages and disadvantages for the TTL system.
It is clear from the above that, for the manufacturing of semiconductor devices, it is critically important that multiple layers of exposure are created such that these layers closely align with each other. Any deviation from this close alignment will result in either faulty or in marginally operational devices. While some overlay errors may be allowed, the continual striving in creating overlying patterns is to make this overlay error as small as possible with the ultimate objective of completely eliminating all overlay errors. For many of the pattern creation activities, a masking system is used whereby a pattern is placed on a reticle. It is at this time of value to reiterate the meaning of the concept of mask and reticle: a mask is a patterning tool that contains a pattern that must be created over an entire surface of a wafer in one exposure, a reticle is a pattern creation tool that contains pattern images that must be stepped and repeated in order to expose an entire surface of a wafer. For overlying layers that are created in or on a semiconductor surface, successive masks are aligned by using alignment marks on each of the masks that is used for the various layers and aligning these alignment marks with the mark or marking pattern of the reticle. This approach assures that each successive layer can be deposited with extreme accuracy and closely aligned with preceding patterns that have been created on the semiconductor surface.
Wafer stepper tools have long been used for the purpose of exposing patterns in a step-and-repeat pattern by imaging several successive exposures of portions of a wafer surface and, in this manner, to cover the entire wafer surface. Wafer stepper tools typically align using an exposure mask with respect to a wafer. The wafer stepper tool uses an image, that is observed and transmitted by a camera, projects the image onto the reticle from where the image gets imprinted onto the surface of a photo sensitive layer such as photoresist. The camera typically, for increased accuracy, magnifies the observed image (by a factor of 5). The position of the reticle with respect to the semiconductor surface that must be exposed is controlled by alignment marks on the surface of the wafer, these alignment marks are used to accurately position the reticle with respect to the semiconductor surface.
For high speed, automated semiconductor manufacturing facilities, the alignment of wafers within wafer stepping tools is accomplished by optical means by using, for instance, a laser beam that is aimed at the semiconductor surface, typically the surface of a substrate. A mark has been provided in this surface by conventional methods of photolithography, for the alignment mark to provide dependable alignment capabilities the mark must be deep enough (that is have a sufficiently high step between the bottom of the mark and the surrounding surface) while the surface on which the optical beam impacts and from which this beam is reflected must have good refractive capabilities. At the time of alignment and for alignment purposes, the optical beam is moved across the surface that contains the alignment mark, the light that is reflected by the surface is captured and observed. The pattern or behavior of the reflected light indicates where the impacting light beam is with respect to the alignment mark and can therefore be used to locate the alignment mark and, finally, to align the wafer within the wafer stepper tool.
The invention addresses the aspect of wafer alignment where, for a stepper and scanner tool, an alignment mark is created by using a special alignment mask. This requires that the special mask be loaded onto the reticle stack after which the alignment mark is printed. This process therefore requires a special alignment mask while this mask, before the alignment mark can be printed, must be aligned in the reticle stack. This latter step is a time consuming process, which traditionally results in a negative cost impact on the manufacturing of the semiconductor devices and is therefore to be avoided. The invention provides a method whereby a (zero-layer or containing no layer pattern) reticle containing an alignment mark is mounted directly on the reticle stack. The optical scanner can now print the alignment mark directly, eliminating time-consuming operations of mounting a special alignment mark mask and aligning the reticle for the special alignment mark.
U.S. Pat No. 6,083,650 (Ogusu et al.) shows a method for forming alignment marks by using a reticle.
U.S. Pat. No. 5,902,452 (Chen et al.) shows a method to form alignment marks using a dry etch.
U.S. Pat. No. 5,837,404 (Lu) discloses a method for forming the zero layer mask.
U.S. Pat. No. 5,893,744 (Wang) shows a method for forming the zero layer mark for alignment.
A principle objective of the invention is to simplify the process of using alignment marks.
Yet another objective of the invention is to remove the need for a conventional reticle in order to create alignment marks.
A still further objective of the invention is to provide a zero-layer reticle that is mounted directly on the reticle stage.
In accordance with the objectives of the invention a new method is provided for the use of alignment marks. In prior art methods, a combination mask is mounted in a mask holder. The combination mask contains multiple, different alignment marks for different purposes and steps in a semiconductor processing sequence. This mark is printed onto the surface of a wafer. Using the method of the invention, a reticle is used that does not contain any patterns (a zero-layer reticle), on this zero-layer reticle an alignment mark is created. This zero-layer alignment mark is referred to as the zero-mark alignment mark, this alignment mark can be printed directly onto the wafer surface. Under the invention, the zero-layer reticle takes the place of the prior art mask holder, on the zero-layer reticle an alignment mark is created that can be directly printed from the zero-layer reticle onto the surface of a wafer. The zero-layer reticle further contains a multiplicity of production alignment marks in a location that is fixed with respect to the alignment mark. The location of the alignment marks therefore corresponds to a location of each alignment mark that belongs to the multiplicity of production alignment marks.